One type of memory known in the art is dynamic random access memory (DRAM). DRAM, typically, includes a plurality of memory banks. Each memory bank includes one or more arrays of memory cells. The memory cells in each array of memory cells are arranged in rows and columns, with the rows extending along an x-direction and the columns extending along a y-direction. Conductive word lines extend across an array of memory cells along the x-direction and conductive bit lines extend across an array of memory cells along the y-direction. A memory cell is located at each cross-point of a word line and a bit line. Memory cells are accessed using a row address and a column address.
Each of the memory cells in an array of memory cells includes a capacitor and a transistor. The capacitor is electrically coupled through the transistor to one of the bit lines. The control input of the transistor is electrically coupled to one of the word lines. The transistor is switched on (conducting) to access the capacitor and off (non-conducting) to capture a voltage level on the capacitor. The capacitor is charged to a high voltage level that can represent a logic one or discharged to a low voltage level that can represent a logic zero.
Each bit line is electrically coupled to a sense amplifier and precharged to a precharge voltage level by a precharge voltage source. Prior to a read or write operation, the precharge voltage source is removed from the bit line and the bit line floats at the precharge voltage level. The sense amplifier can be a differential amplifier with one input electrically coupled to a bit line and the other input electrically coupled to a reference voltage level, such as the precharge voltage level.
During a read operation, the word line is activated to turn on the transistor. The voltage level stored on the capacitor is passed to the floating bit line to change the voltage level on the bit line to either a higher or lower voltage level than the precharge voltage level. The sense amplifier compares the voltage level on the bit line to the reference voltage level and provides a corresponding high or low voltage level response. In addition, the sense amplifier provides the response back to the memory cell through the bit line to charge or discharge the capacitor and store the voltage level just read back on the capacitor. The word line is deactivated to turn off the transistor and the bit line is precharged to the precharge voltage level to prepare for the next operation.
During a write operation, the word line is activated to turn on the transistor to access the capacitor through the bit line. Typically, a write driver circuit overdrives the sense amplifier to charge or discharge the capacitor through the bit line and transistor. The word line is deactivated to turn off the transistor and store the captured value on the capacitor. The bit line is precharged to the precharge voltage level to prepare for the next operation.
During normal operation, referred to as normal mode, each memory bank is accessed independently of the other memory banks. A read or write command is issued and one memory bank is addressed to read or write memory cells in the selected memory bank. The other memory banks are precharged as the selected memory bank is accessed. After data has been read from or written to the selected memory bank, the bit lines of the selected memory bank are precharged to the precharge voltage level to complete the read or write operation. Another command is issued to read or write memory cells in the same or another memory bank. Issuing one command to access and precharge one memory bank at a time is time consuming and, if used to test all of the memory banks, can lead to testing costs that exceed costs the market can bear.
During testing of the memory, the memory can be put into a special mode, referred to as test mode. In test mode, one read or write command is issued to simultaneously access a plurality of memory banks. The memory automatically transfers data to or from each of the simultaneously accessed memory banks in response to one read or write command. Multiple commands are not needed to access multiple memory banks. Data is transferred to or from each of the simultaneously accessed memory banks in data bursts that are time multiplexed or interleaved during the read or write operation. For example, during a test mode read operation on a two-memory bank DRAM, a first data bit from the first memory bank is provided on a data line followed by a first data bit from the second memory bank. Next, a second data bit from the first memory bank is provided on the data line followed by a second data bit from the second memory bank. The data burst from the first memory bank is not completed before beginning the data burst from the second memory bank. Test mode operation decreases testing time as compared to normal mode operation. However, precharging the memory banks at the appropriate time and in the proper sequence can be a difficult task.